MOSFETs, FinFets & GAA Device Physics (2 days)

This three day course is designed to provide practical and physical understanding of VLSI devices and technology. It is intended to give the participants insights into the physics of semiconductor devices, characterization techniques and device technology. The emphasis will be on the problems (and solutions) of CMOS devices when they are scaled to deep-submicron regime. This course is designed to enable the students to: (1) Refresh the physics and design of submicron devices with the emphasis on reliability issues. (2) Review various potential high-field effects due to device scaling (e.g. hot-carrier degradation). (3) Determine the advantages as well as shortcomings of various submicron device structures and processes. (4) Characterize these devices for both fundamental understanding and reliability evaluation.  

What the Course Covers:

• Effects of Technology Scaling on VLSI Devices and Basic Review
• Review semiconductor physics and pn junctions
• Introduce technology scaling trend.
• MOS Devices and Process Optimization
• Explain MOS capacitor, process and characterization; effects of gate oxide process on oxide integrity
• MOSFET,  FinFet, GAA Scaling Effects and Process/device Solutions
• Explain subthreshold characteristics, effective mobility and velocity saturation effects of submicron devices
• Explain short-channel / narrow channel effects and their "reverse" effects; and the solutions
• Describe drain-induced barrier lowering (DIBL) and punch through
• Explain hot-electron effects and LDD Devices; gate induced drain leakage
• Describe CMOS latch up and the process / design solutions
• Explain poly-depletion and quantum mechanical effects
• Describe silicon-on-insulator technology and devices (e.g. FinFETs)
• Explain strained-Si and SiGe devices
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