Strain Silicon Technology

This course is designed to provide practical and physical understanding of strained-silicon devices, technology and applications. It is intended to give the participants insights into the physics of strained silicon devices, fabrication processes, characterization techniques and mobility enhancement. The emphasis will be on the advantages and challenges of strained silicon CMOS devices, especially when they are scaled to deep-submicron regime. This course is designed to enable the students to:
• refresh the physics and design of deep submicron devices
• review the current status of strained silicon technology
• determine the advantages as well as shortcomings of various strain techniques (biaxial vs. uniaxial), device structures and processes
• understand the effects of strain on electron and hole mobility, dopant diffusion, threshold voltage, short channel effects, and subthreshold characteristics
• understand the channel and wafer orientation dependence of strained silicon devices

What the Course Covers:

Review of CMOS technology scaling and short-channel device operation
Biaxial strained Si on relaxed SiGe
Band diagram and band-offsets
Ge outdiffusion effects
Effects on silicide resistance, VT, SCE, subthreshold swing and DIBL
Self-heating Effects Electron mobility and hole mobility enhancement
Uniaxial strained Si using SiGe S/D and stressed liners
Biaxial - uniaxial strained Si comparison
Effects of stress polarities on mobility SiN stressed liners processes (e.g. spacers, Ge implant)
Embedded SiGe source/drain for compressive strain
Channel orientation dependence Electron / hole mobility enhancement vs. effective field Uniaxial stress using dual stress layers
shallow trench isolation and silicide - uniformity, GOI, etc

Who Should Attend:

Any one wanting an understanding of strain silicon

Next Schedule Date and Location:

Only offer at clients site

Price: $8,900 USD for up to 14 students