Course Overview
This 2-day course outlines the steps to be taken to maximize the probability of successful design of an Application Specific Integrated Circuit (ASIC) design. We explain the differences between the basic ASIC architectures, such as Standard Cell, Gate Arrays, and FPGAs. We will then examine specific design issues that can cause failures along with techniques to avoid them, including design-for-test (DFT) methods, simulation, and overall procedures for testing the chip at final test.
What the Course Covers
ASIC Fundamentals
- What is the definition of an ASIC device?
- ASIC applications and market overview
- Design flow and methodology
ASIC Architectures
- Standard Cell architecture
- Gate Array architecture
- FPGAs (Field-Programmable Gate Arrays)
- Comparison of different architectures
- Selection criteria for each approach
Design Techniques and Issues
- Design Techniques and Issues
- Specific design issues that can cause failures
- Techniques to avoid common design problems
- Design optimization strategies
Synchronous Design
- Synchronous Design principles
- Clock domain considerations
- Timing analysis and constraints
- Clock distribution and skew
Design for Testability
- Design for Testability (DFT) methods
- Scan chain implementation
- Built-in self-test (BIST)
- Boundary scan techniques
- Test coverage optimization
Simulation and Testing
- Simulation methodologies
- Verification strategies
- Testing procedures for chip validation
- Overall procedures for testing the chip at final test
Who Should Attend
Anyone wanting an understanding of ASIC design.