Course Overview
This three day course is designed to provide practical and physical understanding of VLSI devices and technology. It is intended to give the participants insights into the physics of semiconductor devices, characterization techniques and device technology. The emphasis will be on the problems (and solutions) of CMOS devices when they are scaled to deep-submicron regime.
This course is designed to enable the students to: (1) Refresh the physics and design of submicron devices with the emphasis on reliability issues. (2) Review various potential high-field effects due to device scaling (e.g. hot-carrier degradation). (3) Determine the advantages as well as shortcomings of various submicron device structures and processes. (4) Characterize these devices for both fundamental understanding and reliability evaluation.
What You'll Learn
- Effects of Technology Scaling on VLSI Devices and Basic Review
- MOS Devices and Process Optimization
- MOSFET, FinFet, GAA Scaling Effects and Process/Device Solutions
- Short-channel and Narrow Channel Effects
- Hot-electron Effects and Advanced Device Structures
- Silicon-on-Insulator Technology and FinFETs
- Strained-Si and SiGe Devices
Course Modules
Module 1: Technology Scaling and Semiconductor Physics
- Review semiconductor physics and pn junctions
- Introduce technology scaling trends
- Effects of scaling on VLSI device performance
- Basic device physics refresher
Module 2: MOS Devices and Process Optimization
- MOS capacitor fundamentals and characterization
- Gate oxide process and integrity effects
- Process optimization for advanced nodes
- Oxide reliability and breakdown mechanisms
Module 3: MOSFET Scaling Effects and Solutions
- Subthreshold characteristics analysis
- Effective mobility and velocity saturation effects
- Short-channel and narrow channel effects
- Reverse short-channel effects and solutions
Module 4: Advanced Device Effects
- Drain-induced barrier lowering (DIBL)
- Punch through mechanisms
- Hot-electron effects and LDD devices
- Gate induced drain leakage (GIDL)
Module 5: CMOS Reliability and Advanced Effects
- CMOS latch up and process/design solutions
- Poly-depletion effects
- Quantum mechanical effects in scaled devices
- Reliability characterization techniques
Module 6: Advanced Device Architectures
- Silicon-on-insulator (SOI) technology and devices
- FinFET device physics and advantages
- Gate-All-Around (GAA) device structures
- Strained-Si and SiGe device physics
Learning Objectives
This course is designed to enable students to:
- Refresh the physics and design of submicron devices with emphasis on reliability issues
- Review various potential high-field effects due to device scaling (e.g. hot-carrier degradation)
- Determine the advantages as well as shortcomings of various submicron device structures and processes
- Characterize these devices for both fundamental understanding and reliability evaluation
Prerequisites
- Basic knowledge of semiconductor device operation
- Understanding of semiconductor physics fundamentals
- Engineering background preferred
- Familiarity with CMOS technology concepts
Who Should Attend
- Engineers, Technicians and Managers who want to refresh their understanding of submicron CMOS devices
- Device physicists working on advanced technology nodes
- Process engineers involved in device scaling
- Design engineers working with advanced device models
- Anyone seeking insights into ultra-small device physics and reliability
Expert Instructors
Industry veterans with 20+ years of experience in advanced semiconductor device physics and VLSI technology development.